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公开(公告)号：US20240222356A1
公开(公告)日：2024-07-04
申请号：US18149279
申请日：2023-01-03
发明人： James P. Mazza , Jia Zeng , Xuelian Zhu , Navneet K. Jain , Mahbub Rashed , Jacob Mazza
IPC分类号： H01L27/02
CPC分类号： H01L27/0207
摘要： A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.
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公开(公告)号：US11894845B1
公开(公告)日：2024-02-06
申请号：US17898937
申请日：2022-08-30
发明人： Navneet K. Jain , Mahbub Rashed
CPC分类号： H03K3/012 , H03K3/037 , H03K5/01 , H03K2005/00013
摘要： Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.
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公开(公告)号：US20230326520A1
公开(公告)日：2023-10-12
申请号：US17658189
申请日：2022-04-06
IPC分类号： G11C11/419 , G11C11/412 , H03K3/356
CPC分类号： G11C11/419 , G11C11/412 , H03K3/356078 , H03K3/356026
摘要： Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.
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公开(公告)号：US20230282707A1
公开(公告)日：2023-09-07
申请号：US17687941
申请日：2022-03-07
发明人： Navneet K. Jain , Mahbub Rashed
CPC分类号： H01L29/1087 , H01L27/1203 , H01L29/7838
摘要： Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.
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公开(公告)号：US11322200B1
公开(公告)日：2022-05-03
申请号：US17120325
申请日：2020-12-14
发明人： Vivek Raj , Shivraj G. Dharne , Uttam K. Saha , Mahbub Rashed
IPC分类号： G11C11/419 , G11C11/418 , G11C11/412
摘要： A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
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公开(公告)号：US11218137B2
公开(公告)日：2022-01-04
申请号：US16847807
申请日：2020-04-14
发明人： Uttam Saha , Mahbub Rashed
摘要： The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.
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公开(公告)号：US11050414B1
公开(公告)日：2021-06-29
申请号：US16881053
申请日：2020-05-22
发明人： Uttam Saha , Mahbub Rashed
摘要： A dynamic single input-dual output latch includes input, feedback, and output stages. In the input stage, operations are dependent on a clock signal (CLK) and a feedback signal (FB) from the feedback stage. For example, when FB is at a low voltage level and CLK switches to a high voltage level, the input stage enters a data capture mode. Once data has been captured, FB switches back to the high voltage level, placing the input stage in a data hold mode. In the output stage, operations are dependent on CLK but independent of FB. For example, instead of initiating output signal stabilization only after both CLK and FB are at high voltage levels, weak pull-down transistors (including at least one CLK-controlled pull-down transistor) are employed in the output stage to ensure output signal stabilization is initiated after data capture has begun but before FB switches to the high voltage level.
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公开(公告)号：US20230341888A1
公开(公告)日：2023-10-26
申请号：US17726171
申请日：2022-04-21
发明人： Vivek Raj , Sunil Kumar , Shivraj G. Dharne , Mahbub Rashed
CPC分类号： G06F1/10 , G06F15/7839
摘要： An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.
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公开(公告)号：US20230267259A1
公开(公告)日：2023-08-24
申请号：US17679178
申请日：2022-02-24
发明人： Navneet Jain , Mahbub Rashed
IPC分类号： G06F30/392 , G06F30/398
CPC分类号： G06F30/392 , G06F30/398 , G06F2111/20
摘要： Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.
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公开(公告)号：US20230163134A1
公开(公告)日：2023-05-25
申请号：US17533402
申请日：2021-11-23
发明人： Navneet Jain , Nigel Chan , Mahbub Rashed
IPC分类号： H01L27/12
CPC分类号： H01L27/1207
摘要： Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.
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