In example implementations, a computing device is provided. The computing device includes a memory bus, a first memory module connected to a first slot of the memory bus, a second memory module connected to a second slot of the memory bus, and a processor communicatively coupled to the memory bus. The processor is to detect a mixed memory module configuration caused by the first memory module and the second memory module and train the first memory module and the second memory module to operate at a maximum mixed memory module configuration speed.