An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.