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公开(公告)号：US11907559B1
公开(公告)日：2024-02-20
申请号：US17883651
申请日：2022-08-09
发明人： Itay Admon , Uri Kaluzhny , Nir Tasher
CPC分类号： G06F3/0644 , G06F3/0622 , G06F11/1044 , G06F3/0679
摘要： A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.
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2.发明公开公开(公告)号：US20230315598A1
公开(公告)日：2023-10-05
申请号：US17713260
申请日：2022-04-05
发明人： Tal Klein , Ronny Aboutboul , Yoram Avigdor , Erez Glasberg
摘要： An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.
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公开(公告)号：US09978435B1
公开(公告)日：2018-05-22
申请号：US15415489
申请日：2017-01-25
发明人： San-Ha Park
IPC分类号： G11C11/14 , G11C11/406 , G11C11/4091 , G11C11/408 , G11C11/4096 , G11C11/419 , G11C11/417
CPC分类号： G11C11/40615 , G11C5/025 , G11C7/065 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/417 , G11C11/419 , G11C2207/002 , G11C2207/2227
摘要： A memory device includes a memory array including a plurality of memory cells coupled to a plurality of bitlines and a plurality of wordlines and a plurality of sense amplifier circuits coupled to the plurality of bitlines. Each sense amplifier circuit includes a sense amplifier configured to sense and amplify a voltage difference between two of the bitlines coupled thereto. The memory device further includes an address decoder to receive and decode addresses of memory cells to enable corresponding bitlines and wordlines, a refresh controller to control data refreshing of the memory cells, and a mode controller to control the memory device to operate in different operating modes including a deep power down (DPD) mode. The mode controller controls data of a group of the memory cells, sensed by corresponding ones of the sense amplifier circuits, to be latched in the corresponding sense amplifier circuits when entering the DPD mode.
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公开(公告)号：US09641491B2
公开(公告)日：2017-05-02
申请号：US14311396
申请日：2014-06-23
发明人： Uri Kaluzhny , Nir Tasher
CPC分类号： H04L63/0457 , G06F21/85 , H04L9/0662 , H04L9/3242 , H04L9/3247 , H04L63/0428
摘要： A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface.
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公开(公告)号：US09471413B2
公开(公告)日：2016-10-18
申请号：US15004957
申请日：2016-01-24
发明人： Nir Tasher , Uri Kaluzhny , Tsachi Weiser , Valery Teper
CPC分类号： G06F11/0769 , G06F11/073 , G06F11/26 , G06F21/79 , G11C7/24 , G11C29/12 , G11C29/38
摘要： A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.
摘要翻译： 一种在测试模式下操作的存储器件中的方法，包括接收要写入存储器件的向量。 只有当向量属于预定义的一组测试向量时，才将向量写入存储器件。 如果矢量不属于一组测试矢量，则将矢量转换为一个测试矢量，并将转换的矢量写入存储器件。
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公开(公告)号：US20160224417A1
公开(公告)日：2016-08-04
申请号：US14608213
申请日：2015-01-29
发明人： Nir TASHER
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/42 , G11C29/52 , G11C2029/0411
摘要： A method of enhancing error correction in a data storage system, including receiving a data storage system having one or more rows each row having: a set of data bits including a word of data, a first set of error correction bits and a second set of error correction bits or a flag bit or both; each bit can be in a first state or a second state; wherein initially all the bits are in the first state; writing data in a word in the data storage system by changing bits from the first state to the second state; creating an error correction code for the word in the first set of error correction bits; receiving a request to update the word by changing one or more additional bits of the word from the first state to the second state; calculating a new error correction code for the updated word; optionally determining if the new error correction code only requires changing bits of the first set of error correction bits from the first state to the second state, if the determination result is positive then updating the first set of error correction bits; otherwise using the second set of error correction bits and/or the flag bit to reduce the need to rewrite the word because of the error correction code.
摘要翻译： 一种增强数据存储系统中的纠错的方法，包括接收具有一行或多行的数据存储系统，每行具有：一组包括数据字的数据位，第一组纠错位和第二组 纠错位或标志位或两者; 每个位可以处于第一状态或第二状态; 其中最初所有位都处于第一状态; 通过将位从第一状态改变到第二状态来将数据写入数据存储系统中的一个字; 为第一组纠错位中的单词创建纠错码; 通过将所述单词的一个或多个附加位从所述第一状态改变到所述第二状态来接收更新所述单词的请求; 计算更新字的新纠错码; 可选地确定新的纠错码是否仅需要将第一组纠错位的位从第一状态改变到第二状态，如果确定结果为正，则更新第一组纠错位; 否则使用第二组纠错位和/或标志位来减少由于纠错码而重写该字的需要。
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7.发明授权NAND flash memory having internal ECC processing and method of operation thereof 有权具有内部ECC处理的NAND闪存及其操作方法公开(公告)号：US09367392B2
公开(公告)日：2016-06-14
申请号：US14450188
申请日：2014-08-01
发明人： Oron Michael
CPC分类号： G06F11/1068 , G11C16/26 , G11C2029/0411 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27
摘要： A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
摘要翻译： 可以通过使用具有分区数据寄存器和分区缓存寄存器的数据缓冲器，与缓存寄存器相关联的用户可配置内部ECC以及快速坏块管理来实现连续读操作。 在数据读取操作期间，ECC状态可由ECC状态位指示。 例如，状态（1：1）可能指示连续读取模式，整个数据输出在多页中包含超过4位错误/页面。 但是，可能希望知道每个页面或每个页面分区的ECC状态。 对于前者，可以在页面输出结束的状态寄存器中确定整个页面的ECC状态。 对于后者，可以在输出相应的页面分区之前确定并输出每个页面分区的ECC状态。
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公开(公告)号：US09343162B2
公开(公告)日：2016-05-17
申请号：US14467077
申请日：2014-08-25
发明人： Nir Tasher , Valery Teper , Dennis Chin Cheng , Boaz Tabachnik
CPC分类号： G11C16/22 , G06F12/1433 , G11C7/24 , G11C16/10
摘要： A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.
摘要翻译： 非易失性存储器（NVM）设备包括被配置为存储数据的NVM阵列和控制逻辑。 控制逻辑被配置为接收用于存储在NVM阵列中的数据值，并且将至少一些所接收的数据值写入到NVM阵列中并且同时写入所接收的至少一些数据值的补码。
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公开(公告)号：US09275738B2
公开(公告)日：2016-03-01
申请号：US14697148
申请日：2015-04-27
发明人： Jongjun Kim , Eungjoon Park
摘要： A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
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10.发明申请公开(公告)号：US20160034351A1
公开(公告)日：2016-02-04
申请号：US14447919
申请日：2014-07-31
发明人： Oron Michael
CPC分类号： G06F11/1072 , G06F11/1048 , G06F11/1064 , G06F12/0246 , G06F12/08 , G06F13/16 , G06F2212/1016 , G06F2212/7202 , G06F2212/7203 , G11C2029/0411
摘要： The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.
摘要翻译： 可以使用用于快速执行的高速缓存程序执行技术对存储器装置中的NAND快闪存储器阵列进行编程。 存储器件包括页缓冲器，其可以被实现为高速缓存寄存器和数据寄存器。 程序数据可以被加载到高速缓存寄存器，其中它可以由纠错码（“ECC”）电路来处理。 此后，高速缓存寄存器中的ECC处理数据可以被复制到数据寄存器，并用于对NAND闪速存储器阵列进行编程。 有利的是，在高速缓存寄存器中ECC处理的数据被复制到数据寄存器之后，高速缓存寄存器可以在其他操作中可用。 特别有益的是，当程序数据的第一页被编程到NAND快闪存储器阵列中时，第二页程序数据可以被加载到高速缓存寄存器和ECC中。
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