- 专利标题: Semiconductor Device and Method For Driving Semiconductor Device
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申请号: US18233172申请日: 2023-08-11
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公开(公告)号: US20230389262A1公开(公告)日: 2023-11-30
- 发明人: Shunpei YAMAZAKI , Hajime KIMURA , Takayuki IKEDA , Kiyoshi KATO , Yuta ENDO , Junpei SUGAO
- 申请人: Semiconductor Energy Laboratory Co., Ltd.
- 申请人地址: JP Kanagawa-ken
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: JP Kanagawa-ken
- 优先权: JP 17113842 2017.06.08
- 主分类号: H10B12/00
- IPC分类号: H10B12/00 ; G11C5/02 ; G11C11/403 ; G11C11/409 ; H01L29/24
摘要:
A semiconductor device with a large storage capacity per unit area is provided.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.
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