公开(公告)号：US20240423096A1

公开(公告)日：2024-12-19

申请号：US18691163

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/85

Abstract: A semiconductor device with high storage capacity and low power consumption is provided. The semiconductor device includes first to third conductors, first and second transistors, and an MTJ element. The MTJ element includes a free layer and a fixed layer. In the semiconductor device, the first conductor, the second conductor, the free layer, the fixed layer, the first and second transistors, and the third conductor are provided in this order from the bottom. In particular, in a plan view, the third conductor is positioned in a region overlapping with the first conductor. The first conductor is electrically connected to the second conductor, and the second conductor is electrically connected to the free layer and a first terminal of the first transistor. The fixed layer is electrically connected to a first terminal of the second transistor, and a second terminal of the first transistor is electrically connected to a second terminal of the second transistor and the third conductor. The first transistor and the second transistor each include a metal oxide in a channel formation region.

公开(公告)号：US20240304231A1

公开(公告)日：2024-09-12

申请号：US18657376

申请日：2024-05-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US20240063797A1

公开(公告)日：2024-02-22

申请号：US18240389

申请日：2023-08-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/17728 ,  H03K19/173 ,  H03K19/17758 ,  H03K19/17772

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17758 ,  H03K19/17772

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20230413587A1

公开(公告)日：2023-12-21

申请号：US18242210

申请日：2023-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H10B99/00 ,  H01L27/105 ,  H01L27/12 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  H01L29/24 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/105 ,  H01L27/1225 ,  H10B12/00 ,  H10B41/20 ,  G11C13/0007 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H10B41/70

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20230309308A1

公开(公告)日：2023-09-28

申请号：US18129120

申请日：2023-03-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20230253031A1

公开(公告)日：2023-08-10

申请号：US18135779

申请日：2023-04-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H10B12/00

CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C5/063 ,  H10B12/30

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

公开(公告)号：US20230230994A1

公开(公告)日：2023-07-20

申请号：US18105005

申请日：2023-02-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Takanori MATSUZAKI ,  Hajime KIMURA ,  Shunpei YAMAZAKI

IPC: H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  H04N25/771 ,  H04N25/772 ,  H10B99/00

CPC classification number: H01L27/14634 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H04N25/771 ,  H04N25/772 ,  H10B99/00

Abstract: An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

公开(公告)号：US20220149045A1

公开(公告)日：2022-05-12

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/118 ,  H01L27/115 ,  H01L29/786

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20220139917A1

公开(公告)日：2022-05-05

申请号：US17414614

申请日：2019-11-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H01L27/108 ,  H01L29/786

Abstract: A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

公开(公告)号：US20220085073A1

公开(公告)日：2022-03-17

申请号：US17422312

申请日：2019-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Yuto YAKUBO ,  Yuki OKAMOTO ,  Seiya SAITO ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.