- 专利标题: INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCE
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申请号: US17461322申请日: 2021-08-30
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公开(公告)号: US20230062162A1公开(公告)日: 2023-03-02
- 发明人: Jui-Lin Chen , Yu-Kuan Lin , Ping-Wei Wang
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L27/11
- IPC分类号: H01L27/11 ; H01L23/528 ; H01L27/088
摘要:
A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.
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