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    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS
    1.
    发明申请
    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS 有权

    公开(公告)号：US20240414907A1

    公开(公告)日：2024-12-12

    申请号：US18489365

    申请日：2023-10-18

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Wei Wang ,  Jui-Lin Chen ,  Yu-Bey Wu

    IPC: H10B10/00

    Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively, and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. A first frontside source/drain contact is disposed above and electrically couples to a first common source/drain region of the first and second pull-down transistors. A first backside via is disposed under and electrically couples to the first common source/drain region. A first backside metal line is disposed under and electrically couples to the first backside via.

    Memory Device With Jogged Backside Metal Lines
    2.
    发明公开
    Memory Device With Jogged Backside Metal Lines 审中-公开

    公开(公告)号：US20240064950A1

    公开(公告)日：2024-02-22

    申请号：US17890762

    申请日：2022-08-18

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang ,  Yi-Feng Ting ,  Hsin-Wen Su ,  Lien-Jung Hung ,  Ping-Wei Wang

    IPC: H01L27/11

    CPC classification number: H01L27/1104

    Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

    Stable SRAM cell
    3.
    发明授权
    Stable SRAM cell 有权

    公开(公告)号：US08908409B2

    公开(公告)日：2014-12-09

    申请号：US14285410

    申请日：2014-05-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC: G11C15/00 ,  G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    Stable SRAM Cell
    4.
    发明申请
    Stable SRAM Cell 有权

    公开(公告)号：US20140254248A1

    公开(公告)日：2014-09-11

    申请号：US14285410

    申请日：2014-05-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES
    6.
    发明公开
    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20240306359A1

    公开(公告)日：2024-09-12

    申请号：US18364842

    申请日：2023-08-03

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

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