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    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES
    1.
    发明公开
    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20240306359A1

    公开(公告)日：2024-09-12

    申请号：US18364842

    申请日：2023-08-03

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC分类号： H10B10/00

    CPC分类号： H10B10/125

    摘要： A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

    Static Random Access Memory (SRAM) Cell and Method for Forming Same
    7.
    发明申请
    Static Random Access Memory (SRAM) Cell and Method for Forming Same 有权
    静态随机存取存储器（SRAM）单元及其形成方法

    公开(公告)号：US20130299917A1

    公开(公告)日：2013-11-14

    申请号：US13940888

    申请日：2013-07-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Lie-Yong Yang ,  Feng-Ming Chang ,  Chang-Ta Yang ,  Ping-Wei Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11 ,  H01L27/1104

    摘要： An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

    摘要翻译： 实施例是用于形成静态随机存取存储器（SRAM）单元的方法。 该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。 晶体管的有源区的纵轴是平行的。 第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。 第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。 第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。

    INTEGRATION OF MEMORY CELL AND LOGIC CELL
    8.
    发明公开
    INTEGRATION OF MEMORY CELL AND LOGIC CELL 审中-公开

    公开(公告)号：US20240306361A1

    公开(公告)日：2024-09-12

    申请号：US18349298

    申请日：2023-07-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ping-Wei Wang ,  Lien-Jung Hung ,  Jui-Lin Chen

    IPC分类号： H10B10/00

    CPC分类号： H10B10/18 ,  H10B10/125

    摘要： A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.

    SRAM design with four-poly-pitch
    10.
    发明授权
    SRAM design with four-poly-pitch 有权

    公开(公告)号：US12046276B2

    公开(公告)日：2024-07-23

    申请号：US18306757

    申请日：2023-04-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih-Chuan Yang ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Ping-Wei Wang

    IPC分类号： G11C11/412 ,  H10B10/00

    CPC分类号： G11C11/412 ,  H10B10/12

    摘要： One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.