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    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES
    3.
    发明公开
    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20240306359A1

    公开(公告)日：2024-09-12

    申请号：US18364842

    申请日：2023-08-03

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

    Static Random Access Memory (SRAM) Cell and Method for Forming Same
    9.
    发明申请
    Static Random Access Memory (SRAM) Cell and Method for Forming Same 有权
    静态随机存取存储器（SRAM）单元及其形成方法

    公开(公告)号：US20130299917A1

    公开(公告)日：2013-11-14

    申请号：US13940888

    申请日：2013-07-12

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Lie-Yong Yang ,  Feng-Ming Chang ,  Chang-Ta Yang ,  Ping-Wei Wang

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11 ,  H01L27/1104

    Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

    Abstract translation: 实施例是用于形成静态随机存取存储器（SRAM）单元的方法。 该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。 晶体管的有源区的纵轴是平行的。 第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。 第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。 第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。

    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS
    10.
    发明申请
    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS 有权

    公开(公告)号：US20240414907A1

    公开(公告)日：2024-12-12

    申请号：US18489365

    申请日：2023-10-18

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Wei Wang ,  Jui-Lin Chen ,  Yu-Bey Wu

    IPC: H10B10/00

    Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively, and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. A first frontside source/drain contact is disposed above and electrically couples to a first common source/drain region of the first and second pull-down transistors. A first backside via is disposed under and electrically couples to the first common source/drain region. A first backside metal line is disposed under and electrically couples to the first backside via.

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