- 专利标题： GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE
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申请号： US17445856申请日： 2021-08-25
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公开(公告)号： US20230073078A1公开(公告)日： 2023-03-09
- 发明人: Willy Rachmady , Sudipto Naskar , Cheng-Ying Huang , Gilbert Dewey , Marko Radosavljevic , Nicole K. Thomas , Patrick Morrow , Urusa Alaan
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H01L27/12
- IPC分类号： H01L27/12
摘要：
An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.
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