Invention Application
- Patent Title: METHOD FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH SIZE-REDUCED SOURCE/DRAIN EPITAXY
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Application No.: US18071876Application Date: 2022-11-30
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Publication No.: US20230100196A1Publication Date: 2023-03-30
- Inventor: Rock Hyun BAEK , Jun Sik YOON , Jin Su JEONG , Seung Hwan LEE
- Applicant: POSTECH Research and Business Development Foundation
- Applicant Address: KR Pohang-si
- Assignee: POSTECH Research and Business Development Foundation
- Current Assignee: POSTECH Research and Business Development Foundation
- Current Assignee Address: KR Pohang-si
- Priority: KR10-2019-0074877 20190624
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/10 ; H01L29/49 ; H01L29/51 ; H01L29/66 ; H01L29/78

Abstract:
Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.
Public/Granted literature
- US11894424B2 Method for fabricating a field-effect transistor with size-reduced source/drain epitaxy Public/Granted day:2024-02-06
Information query
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