Invention Application
- Patent Title: PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS
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Application No.: US17485217Application Date: 2021-09-24
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Publication No.: US20230100228A1Publication Date: 2023-03-30
- Inventor: Gerald PASDAST , Sathya Narasimman TIAGARAJ , Adel A. ELSHERBINI , Tanay KARNIK , Dileep KURIAN , Julien SEBOT
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/48

Abstract:
Embodiments disclosed herein include dies and die modules. In an embodiment, a die comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment the substrate comprises a semiconductor material. In an embodiment, first bumps with a first pitch are on the first surface of the substrate. In an embodiment, a first layer surrounds the first bumps, where the first layer comprises a dielectric material. In an embodiment, second bumps with a second pitch are on the substrate. In an embodiment, the second pitch is greater than the first pitch. In an embodiment, a second layer surrounds the second bumps, where the second layer comprises a dielectric material.
Public/Granted literature
- US1257889A Printer's quoin. Public/Granted day:1918-02-26
Information query
IPC分类: