公开(公告)号：US20230100228A1

公开(公告)日：2023-03-30

申请号：US17485217

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gerald PASDAST ,  Sathya Narasimman TIAGARAJ ,  Adel A. ELSHERBINI ,  Tanay KARNIK ,  Dileep KURIAN ,  Julien SEBOT

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Embodiments disclosed herein include dies and die modules. In an embodiment, a die comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment the substrate comprises a semiconductor material. In an embodiment, first bumps with a first pitch are on the first surface of the substrate. In an embodiment, a first layer surrounds the first bumps, where the first layer comprises a dielectric material. In an embodiment, second bumps with a second pitch are on the substrate. In an embodiment, the second pitch is greater than the first pitch. In an embodiment, a second layer surrounds the second bumps, where the second layer comprises a dielectric material.

公开(公告)号：US20210398906A1

公开(公告)日：2021-12-23

申请号：US16910023

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gerald PASDAST ,  Juan ZENG ,  Peipei WANG ,  Ahmad SIDDIQUI ,  Lakshmipriya SESHAN

IPC: H01L23/538 ,  H01L23/00

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

公开(公告)号：US20230095914A1

公开(公告)日：2023-03-30

申请号：US17485211

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gerald PASDAST ,  Sathya Narasimman TIAGARAJ ,  Adel A. ELSHERBINI ,  Tanay KARNIK ,  Robert MUNOZ ,  Kevin SAFFORD

IPC: G01R31/317 ,  G01R31/28

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.

公开(公告)号：US20230130935A1

公开(公告)日：2023-04-27

申请号：US18088476

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Adel ELSHERBINI ,  Mauro KOBRINSKY ,  Shawna LIFF ,  Johanna SWAN ,  Gerald PASDAST ,  Sathya Narasimman TIAGARAJ

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US20230100375A1

公开(公告)日：2023-03-30

申请号：US17485198

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gerald PASDAST ,  Sathya Narasimman TIAGARAJ ,  Adel A. ELSHERBINI

IPC: H01L25/065 ,  H01L23/00

Abstract: Embodiments disclosed herein include die modules and electronic packages. In an embodiment, a die module comprises a base die where the base die comprises a functional block. In an embodiment, the die module further comprises a chiplet coupled to the base die proximate to the functional block. In an embodiment, the chiplet comprises similar functionality as the functional block.