Invention Application
- Patent Title: SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
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Application No.: US18088476Application Date: 2022-12-23
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Publication No.: US20230130935A1Publication Date: 2023-04-27
- Inventor: Adel ELSHERBINI , Mauro KOBRINSKY , Shawna LIFF , Johanna SWAN , Gerald PASDAST , Sathya Narasimman TIAGARAJ
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/528

Abstract:
An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
Information query
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