Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer. The passive device die includes: a second substrate including a front side and a back side that are opposite to each other, the front side of the second substrate facing the front side of the first substrate; an interlayer dielectric layer on the front side of the second substrate, the interlayer dielectric layer including at least one hole; a passive device in the hole; and a second wiring layer on the passive device, wherein the second wiring layer faces and is connected to the first wiring layer.