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公开(公告)号：US20210296229A1
公开(公告)日：2021-09-23
申请号：US17340584
申请日：2021-06-07
发明人： Jinho PARK , Shaofeng DING , Yongseung BANG , Jeong Hoon AHN
IPC分类号： H01L23/522 , H01L49/02
摘要： A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.
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公开(公告)号：US20210118696A1
公开(公告)日：2021-04-22
申请号：US15931738
申请日：2020-05-14
发明人： Shaofeng DING , Jeong Hoon AHN , Yun Ki CHOI
摘要： The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.
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公开(公告)号：US20200350248A1
公开(公告)日：2020-11-05
申请号：US16660124
申请日：2019-10-22
发明人： Jinho PARK , Shaofeng DING , Yongseung BANG , Jeong Hoon AHN
IPC分类号： H01L23/535 , H01L27/108
摘要： A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.
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公开(公告)号：US20230154894A1
公开(公告)日：2023-05-18
申请号：US17862496
申请日：2022-07-12
发明人： Jegwan HWANG , Jihyung KIM , Jeong Hoon AHN , Jaehee OH , Shaofeng DING , Won Ji PARK , WooSeong JANG , Seokjun HONG
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L23/528
CPC分类号： H01L25/0657 , H01L24/16 , H01L24/05 , H01L24/13 , H01L25/50 , H01L23/5286 , H01L2224/05567 , H01L2224/13025 , H01L2224/16145 , H01L24/73 , H01L2224/73257 , H01L2225/0651 , H01L2225/06517 , H01L24/06 , H01L2224/06181 , H01L24/17 , H01L2224/17181 , H01L2225/06513 , H01L2224/16225 , H01L2225/06544 , H01L25/18
摘要： A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.
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公开(公告)号：US20220028827A1
公开(公告)日：2022-01-27
申请号：US17187985
申请日：2021-03-01
发明人： Shaofeng DING , Jeong Hoon AHN , Yun Ki CHOI
IPC分类号： H01L25/065 , H01L23/64 , H01L23/48 , H01L23/498 , H01L23/528
摘要： A semiconductor device includes an interposer substrate and at least one die mounted on the interposer substrate. The interposer substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, an interlayer insulating layer on the first surface of the semiconductor substrate, a capacitor in a hole penetrating the interlayer insulating layer, an interconnection layer on the interlayer insulating layer, and a through-via extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate. The capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode. A bottom of the hole is distal from the second surface of the semiconductor substrate in relation to the first surface of the semiconductor substrate.
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6.发明申请公开(公告)号：US20190131194A1
公开(公告)日：2019-05-02
申请号：US15997131
申请日：2018-06-04
发明人： Shaofeng DING , Kyoung-woo LEE , In-hwan KIM , Jong-woon LEE
IPC分类号： H01L21/66 , H01L23/498 , H01L21/768 , H01L25/065
摘要： An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group.
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公开(公告)号：US20240164081A1
公开(公告)日：2024-05-16
申请号：US18405736
申请日：2024-01-05
发明人： Shaofeng DING , Jeong Hoon AHN , Yun Ki CHOI
IPC分类号： H10B10/00 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786 , H10B12/00
CPC分类号： H10B10/18 , H01L21/0259 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/092 , H01L29/0665 , H01L29/0847 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/7851 , H01L29/78618 , H01L29/78696 , H10B12/50
摘要： A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.
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公开(公告)号：US20220328404A1
公开(公告)日：2022-10-13
申请号：US17527230
申请日：2021-11-16
发明人： Shaofeng DING , Jeong Hoon AHN , Yun Ki CHOI
IPC分类号： H01L23/528 , H01L25/065 , H01L23/522 , H01L23/48 , H01L21/768
摘要： A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.
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公开(公告)号：US20210125937A1
公开(公告)日：2021-04-29
申请号：US16876502
申请日：2020-05-18
发明人： Shaofeng DING , Jeong Hoon AHN , Yun Ki CHOI
IPC分类号： H01L23/544 , H01L21/48 , H01L25/065 , H01L25/18 , H01L23/498 , H01L25/00
摘要： A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.
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公开(公告)号：US20170207137A1
公开(公告)日：2017-07-20
申请号：US14997823
申请日：2016-01-18
发明人： Shaofeng DING , Junjung KIM , Jeong Hoon AHN
IPC分类号： H01L21/66 , H01L21/78 , H01L23/544 , G01R31/28 , G01R31/26
CPC分类号： H01L22/32 , G01R31/2644 , G01R31/2884 , H01L21/78 , H01L22/34 , H01L23/544 , H01L2223/5446
摘要： A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.
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