公开(公告)号：US20240275387A1

公开(公告)日：2024-08-15

申请号：US18234517

申请日：2023-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Ji PARK ,  Sunoo KIM ,  Jaehee OH ,  Hyungwon KIM ,  WooSeong JANG ,  Taekyung KIM ,  Youngbin HYUN

IPC: H03K19/08

CPC classification number: H03K19/08

Abstract: A logic device includes a substrate; at least one first insulating layer on the substrate; a second insulating layer on the at least one first insulating layer; and a capacitor portion in the at least one first insulating layer and the second insulating layer, wherein the at least one first insulating layer includes a plurality of through-holes, the capacitor portion includes a capacitor structure including a lower electrode, a dielectric film, and an upper electrode, and the capacitor structure continuously extends along the inside of the plurality of through-holes and along an upper surface of the at least one first insulating layer around the plurality of through-holes.

公开(公告)号：US20230154894A1

公开(公告)日：2023-05-18

申请号：US17862496

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jegwan HWANG ,  Jihyung KIM ,  Jeong Hoon AHN ,  Jaehee OH ,  Shaofeng DING ,  Won Ji PARK ,  WooSeong JANG ,  Seokjun HONG

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/05 ,  H01L24/13 ,  H01L25/50 ,  H01L23/5286 ,  H01L2224/05567 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L24/73 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L24/06 ,  H01L2224/06181 ,  H01L24/17 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2224/16225 ,  H01L2225/06544 ,  H01L25/18

Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

公开(公告)号：US20250149478A1

公开(公告)日：2025-05-08

申请号：US18630470

申请日：2024-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho KIM ,  Sunoo KIM ,  Jaehee OH

IPC: H01L23/00

Abstract: A semiconductor package includes: a first substrate that comprises a central area and a peripheral area surrounding the central area; a first pad on the first substrate in the central area; a second pad on the first substrate in the peripheral area; a first solder on and coupled to the first pad; and a second solder on and coupled to the second pad, wherein the first pad has a first recess from a top surface of the first pad, wherein the second pad has a second recess from a top surface of the second pad, wherein a width of the second recess is greater than a width of the first recess, and wherein a volume of the second solder is greater than a volume of the first solder.

公开(公告)号：US20250022758A1

公开(公告)日：2025-01-16

申请号：US18424111

申请日：2024-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho KIM ,  Sunoo KIM ,  Jinwoo KIM ,  Boin NOH ,  Sejun PARK ,  Jaehee OH

IPC: H01L21/66 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

公开(公告)号：US20230131382A1

公开(公告)日：2023-04-27

申请号：US17843594

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng DING ,  Jihyung KIM ,  Won Ji PARK ,  Jeong Hoon AHN ,  Jaehee OH ,  Yun Ki CHOI

IPC: H01L27/06 ,  H01L25/07 ,  H01L27/02

Abstract: Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer. The passive device die includes: a second substrate including a front side and a back side that are opposite to each other, the front side of the second substrate facing the front side of the first substrate; an interlayer dielectric layer on the front side of the second substrate, the interlayer dielectric layer including at least one hole; a passive device in the hole; and a second wiring layer on the passive device, wherein the second wiring layer faces and is connected to the first wiring layer.