Invention Application
- Patent Title: HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
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Application No.: US18089227Application Date: 2022-12-27
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Publication No.: US20230134049A1Publication Date: 2023-05-04
- Inventor: Debendra MALLIK , Ravindranath MAHAJAN , Robert SANKMAN , Shawna LIFF , Srinivas PIETAMBARAM , Bharat PENMECHA
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/538

Abstract:
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
Public/Granted literature
- US11824018B2 Heterogeneous nested interposer package for IC chips Public/Granted day:2023-11-21
Information query
IPC分类: