公开(公告)号：US20200006293A1

公开(公告)日：2020-01-02

申请号：US16024700

申请日：2018-06-29

申请人： Intel Corporation

发明人： Robert SANKMAN ,  Sanka GANESAN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Lizabeth KESER

IPC分类号： H01L25/065

摘要： Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US20190206814A1

公开(公告)日：2019-07-04

申请号：US15859316

申请日：2017-12-29

申请人： Intel Corporation

发明人： Yikang DENG ,  Robert SANKMAN

IPC分类号： H01L23/64 ,  H01L23/00 ,  H01F27/28 ,  H05K1/02

CPC分类号： H01L23/645 ,  H01F27/28 ,  H01L24/16 ,  H01L2224/16265 ,  H01L2924/1427 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/025

摘要： Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.

公开(公告)号：US20240128205A1

公开(公告)日：2024-04-18

申请号：US18397915

申请日：2023-12-27

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

摘要： Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20200303309A1

公开(公告)日：2020-09-24

申请号：US16356442

申请日：2019-03-18

申请人： Intel Corporation

发明人： Robert SANKMAN ,  Robert MAY

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

摘要： Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

公开(公告)号：US20240234245A1

公开(公告)日：2024-07-11

申请号：US18612949

申请日：2024-03-21

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/522 ,  H01L23/538 ,  H01L25/07

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20210028087A1

公开(公告)日：2021-01-28

申请号：US16522443

申请日：2019-07-25

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihau TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20200328139A1

公开(公告)日：2020-10-15

申请号：US16379619

申请日：2019-04-09

申请人： Intel Corporation

发明人： Chia-Pin CHIU ,  Robert SANKMAN ,  Pooya TADAYON

IPC分类号： H01L23/473 ,  H05K7/20 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

摘要： Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.

公开(公告)号：US20240145395A1

公开(公告)日：2024-05-02

申请号：US18406018

申请日：2024-01-05

申请人： Intel Corporation

发明人： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16225

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20230253332A1

公开(公告)日：2023-08-10

申请号：US18135067

申请日：2023-04-14

申请人： Intel Corporation

发明人： Robert SANKMAN ,  Robert MAY

IPC分类号： H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/50 ,  H01L25/0655 ,  H01L21/4857 ,  H01L23/5386

摘要： Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

公开(公告)号：US20230134049A1

公开(公告)日：2023-05-04

申请号：US18089227

申请日：2022-12-27

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

摘要： Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.