Invention Publication
- Patent Title: REDUCING DUTY CYCLE MISMATCH OF CLOCKS FOR CLOCK TRACKING CIRCUITS
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Application No.: US18167722Application Date: 2023-02-10
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Publication No.: US20240007111A1Publication Date: 2024-01-04
- Inventor: Waleed El-halwagy , Youcef Fouzar , Kristopher Kshonze , William Roberts , Faizal Warsalee
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Main IPC: H03L7/081
- IPC: H03L7/081 ; H03K5/156

Abstract:
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.
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