公开(公告)号：US20240056087A1

公开(公告)日：2024-02-15

申请号：US18448783

申请日：2023-08-11

Applicant: Microchip Technology Incorporated

Inventor： Youcef Fouzar ,  Waleed El-halwagy ,  William Roberts ,  Kristopher Kshonze ,  Faizal Warsalee

IPC: H03L7/099 ,  H03L7/10

CPC classification number: H03L7/0991 ,  H03L7/104

Abstract: A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.

公开(公告)号：US20240007093A1

公开(公告)日：2024-01-04

申请号：US18167716

申请日：2023-02-10

Applicant: Microchip Technology Incorporated

Inventor： Waleed El-halwagy ,  Youcef Fouzar ,  Kristopher Kshonze ,  William Roberts ,  Faizal Warsalee

IPC: H03K5/156 ,  H03K7/08 ,  H03K5/135

CPC classification number: H03K5/1565 ,  H03K7/08 ,  H03K5/135

Abstract: One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.

公开(公告)号：US20240007111A1

公开(公告)日：2024-01-04

申请号：US18167722

申请日：2023-02-10

Applicant: Microchip Technology Incorporated

Inventor： Waleed El-halwagy ,  Youcef Fouzar ,  Kristopher Kshonze ,  William Roberts ,  Faizal Warsalee

IPC: H03L7/081 ,  H03K5/156

CPC classification number: H03L7/0812 ,  H03K5/1565

Abstract: One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.

公开(公告)号：US20240004420A1

公开(公告)日：2024-01-04

申请号：US18333827

申请日：2023-06-13

Applicant: Microchip Technology Incorporated

Inventor： Youcef Fouzar ,  Waleed El-halwagy ,  William Roberts ,  Kristopher Kshonze ,  Faizal Warsalee

IPC: G06F1/12 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/10

Abstract: One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.