Invention Publication
- Patent Title: SEMICONDUCTOR PACKAGE STRUCTURE
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Application No.: US18331394Application Date: 2023-06-08
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Publication No.: US20240014143A1Publication Date: 2024-01-11
- Inventor: Yi-Lin TSAI , Kun-Ting HUNG , Yin-Fa CHEN , Chi-Yuan CHEN , Wen-Sung HSU
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsinchu City
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsinchu City
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/31 ; H01L25/065 ; H01L23/00 ; H01L23/498 ; H01L25/10

Abstract:
A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.
Information query
IPC分类: