Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.