公开(公告)号：US20240049481A1

公开(公告)日：2024-02-08

申请号：US18188311

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyeon Kim ,  Takuya Futatsuyama ,  Jooyong Park ,  Beakhyung Cho

IPC: H10B80/00

CPC classification number: H10B80/00

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction and word lines each extending in a second direction and stacked in a vertical direction, word line pads which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width in the first direction and a second width in the second direction. Each of the pass transistors has a first pitch in the first direction and a second pitch in the second direction.

公开(公告)号：US20250069961A1

公开(公告)日：2025-02-27

申请号：US18800813

申请日：2024-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyong Choi ,  Sooyeol Yang ,  Jaeeun Lee ,  Hyuckjoon Kwon ,  Jinwon Choi ,  Takuya Futatsuyama

IPC: H01L21/66 ,  G01R31/28

Abstract: A semiconductor multi-layer structure includes a first semiconductor wafer including a plurality of first pads, a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads, and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.

公开(公告)号：US20240023337A1

公开(公告)日：2024-01-18

申请号：US18118776

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Dohyung Kim ,  Sukkang Sung ,  Takuya Futatsuyama

IPC: H10B43/40 ,  H10B43/10 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B43/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B43/27

Abstract: Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.