A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.