Invention Publication
- Patent Title: MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY
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Application No.: US17884432Application Date: 2022-08-09
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Publication No.: US20240054048A1Publication Date: 2024-02-15
- Inventor: Kishore Kumar Muchherla , Huai-Yuan Tseng , Mustafa N. Kaynak , Akira Goda , Sivagnanam Parthasarathy , Jonathan Scott Parry
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/07

Abstract:
A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.
Public/Granted literature
- US11994947B2 Multi-layer code rate architecture for special event protection with reduced performance penalty Public/Granted day:2024-05-28
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