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公开(公告)号：US12119062B2
公开(公告)日：2024-10-15
申请号：US17884113
申请日：2022-08-09
CPC分类号： G11C16/08 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/10 , G11C16/3459 , G11C16/0483
摘要： Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.
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2.发明公开公开(公告)号：US20240338146A1
公开(公告)日：2024-10-10
申请号：US18743629
申请日：2024-06-14
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.
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公开(公告)号：US12073899B2
公开(公告)日：2024-08-27
申请号：US17536462
申请日：2021-11-29
CPC分类号： G11C29/12005 , G06F18/214 , G06N20/00 , G11C7/02 , G11C29/14 , G11C29/44
摘要： A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
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公开(公告)号：US20240256328A1
公开(公告)日：2024-08-01
申请号：US18419352
申请日：2024-01-22
IPC分类号： G06F9/48
CPC分类号： G06F9/485
摘要： Methods, systems, and apparatuses mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and current bit is selected. In response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion, it is determined that the current bit was flipped in a previous iteration. The flipping of the current bit is bypassed in response to determining the current bit was flipped in the previous iteration.
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5.发明授权公开(公告)号：US11996860B2
公开(公告)日：2024-05-28
申请号：US17829924
申请日：2022-06-01
CPC分类号： H03M13/1108 , H03M13/1128 , H03M13/1148 , H03M13/6511
摘要： A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
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公开(公告)号：US20240045759A1
公开(公告)日：2024-02-08
申请号：US18230360
申请日：2023-08-04
CPC分类号： G06F11/1004 , G06F3/0673 , G06F3/0659 , G06F3/0619
摘要： A method may comprise detecting an error associated with accessing a set of data items. The set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. In response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on RAIN redundancy metadata. In response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on LUN redundancy metadata. In response to determining that the set of data items comprises RAIN redundancy metadata, a first data reconstruction process is performed to regenerate the RAIN redundancy metadata based at least in part on one or more sets of codewords.
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公开(公告)号：US11829729B2
公开(公告)日：2023-11-28
申请号：US16888345
申请日：2020-05-29
发明人： Sean S. Eilert , Shivasankar Gunasekaran , Ameen D. Akel , Dmitri Yudanov , Sivagnanam Parthasarathy
CPC分类号： G06F7/5443 , G06F17/16
摘要： Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.
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公开(公告)号：US20230325273A1
公开(公告)日：2023-10-12
申请号：US18207525
申请日：2023-06-08
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0751 , G06F11/0727
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.
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9.发明授权公开(公告)号：US11775217B2
公开(公告)日：2023-10-03
申请号：US17534850
申请日：2021-11-24
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/26 , G11C16/0483
摘要： A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.
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公开(公告)号：US20230308114A1
公开(公告)日：2023-09-28
申请号：US17706471
申请日：2022-03-28
CPC分类号： H03M13/1108 , H03M13/611
摘要： Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and energy function values are determined for bits of the codeword. A bit flipping criterion is selected using the syndrome information from a plurality of values. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies the bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.
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