Methods, systems, and devices for storing bits, such as N−1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.