发明公开
- 专利标题: PACKAGE ARCHITECTURE WITH INTEGRATED CAPACITORS IN QUASI-MONOLITHIC CHIP LAYERS
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申请号: US17820968申请日: 2022-08-19
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公开(公告)号: US20240063202A1公开(公告)日: 2024-02-22
- 发明人: Adel A. Elsherbini , Thomas Sounart , Henning Braunisch , William J. Lambert , Kaladhar Radhakrishnan , Shawna M. Liff , Mohammad Enamul Kabir , Omkar G. Karhade , Kimin Jun , Johanna M. Swan
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L25/18
- IPC分类号: H01L25/18 ; H01L23/522 ; H01L49/02 ; H01L23/00 ; H01L23/498 ; H01L23/48 ; H01L25/00
摘要:
Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.
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