Invention Publication
- Patent Title: BUTTRESSED FIELD TARGET DESIGN FOR OPTICAL AND E-BEAM BASED METROLOGY TO ENABLE FIRST LAYER PRINT REGISTRATION MEASUREMENTS FOR FIELD SHAPE MATCHING AND RETICLE STITCHING IN HIGH NA LITHOGRAPHY
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Application No.: US17896105Application Date: 2022-08-26
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Publication No.: US20240069447A1Publication Date: 2024-02-29
- Inventor: Deepak SELVANATHAN , William T. BLANTON , Martin WEISS
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G03F9/00

Abstract:
An apparatus of manufacturing a semiconductor device is provided. The apparatus including a controller configured to: expose a first region of a photoresist layer with a light pattern, expose a second region of the photoresist layer with at least in part the same light pattern, wherein the second region and the first region overlap in an overlap region of the photoresist layer, and wherein light pattern is configured to form, in exposing the first region, a first portion of individual markings in the overlap region of the photoresist layer, and to form, in exposing the second region, a second portion of individual markings in the overlap region of the photoresist layer. By measuring the composite pattern formed in photoresist by overlapping the first exposure with the second exposure, the relative position of the two exposures can be determined and controlled.
Information query
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