公开(公告)号：US20240363628A1

公开(公告)日：2024-10-31

申请号：US18767458

申请日：2024-07-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240069447A1

公开(公告)日：2024-02-29

申请号：US17896105

申请日：2022-08-26

Applicant: Intel Corporation

Inventor： Deepak SELVANATHAN ,  William T. BLANTON ,  Martin WEISS

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70633 ,  G03F9/7084 ,  G03F9/7088 ,  G03F7/2022

Abstract: An apparatus of manufacturing a semiconductor device is provided. The apparatus including a controller configured to: expose a first region of a photoresist layer with a light pattern, expose a second region of the photoresist layer with at least in part the same light pattern, wherein the second region and the first region overlap in an overlap region of the photoresist layer, and wherein light pattern is configured to form, in exposing the first region, a first portion of individual markings in the overlap region of the photoresist layer, and to form, in exposing the second region, a second portion of individual markings in the overlap region of the photoresist layer. By measuring the composite pattern formed in photoresist by overlapping the first exposure with the second exposure, the relative position of the two exposures can be determined and controlled.

公开(公告)号：US20220093589A1

公开(公告)日：2022-03-24

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.