Invention Publication
- Patent Title: AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES
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Application No.: US17897910Application Date: 2022-08-29
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Publication No.: US20240070008A1Publication Date: 2024-02-29
- Inventor: Jay Sarkar , Ipsita Ghosh , Vamsi Pavan Rayaprolu
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Main IPC: G06F11/07
- IPC: G06F11/07

Abstract:
Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
Public/Granted literature
- US11994936B2 Automated optimization of error-handling flows in memory devices Public/Granted day:2024-05-28
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