A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.