公开(公告)号：US20240079057A1

公开(公告)日：2024-03-07

申请号：US17930279

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Paolo Tessariol ,  Umberto Maria Meotto

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US11818893B2

公开(公告)日：2023-11-14

申请号：US17819009

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H01L2223/54426

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US20220223613A1

公开(公告)日：2022-07-14

申请号：US17146193

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US20240071497A1

公开(公告)日：2024-02-29

申请号：US17898827

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Umberto Maria Meotto ,  Domenico Tuzi

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.

公开(公告)号：US20240057328A1

公开(公告)日：2024-02-15

申请号：US17819575

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Anna Maria Conti ,  Paolo Tessariol

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11551

CPC classification number: H01L27/11524 ,  H01L27/11582 ,  H01L27/11551 ,  H01L29/0649

Abstract: A microelectronic device includes a stack structure including tiers each including insulative material and conductive material vertically adjacent the insulative material. The stack structure divided into at least two blocks separated from one another. The microelectronic device further includes at least one slot structure horizontally interposed between the at least two blocks of the stack structure. The at least one slot structure including additional insulative material and at least one contact structure extending through the additional insulative material to source tier underlying the stack structure.

公开(公告)号：US20230317604A1

公开(公告)日：2023-10-05

申请号：US17657264

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76877

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases comprises steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

公开(公告)号：US09356237B2

公开(公告)日：2016-05-31

申请号：US14738453

申请日：2015-06-12

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto Maria Meotto ,  Giorgio Servalli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

公开(公告)号：US12185549B2

公开(公告)日：2024-12-31

申请号：US18209204

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US20240099007A1

公开(公告)日：2024-03-21

申请号：US18525652

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20240071918A1

公开(公告)日：2024-02-29

申请号：US17822421

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Indra V. Chary ,  Richard J. Hill ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.