公开(公告)号：US20230017305A1

公开(公告)日：2023-01-19

申请号：US17730325

申请日：2022-04-27

申请人： Micron Technology, Inc.

发明人： Mattia Cichocki ,  Vladimir Mikhalev ,  Phani Bharadwaj Vanguri ,  James Eric Davis ,  Kenneth William Marr ,  Chiara Cerafogli ,  Michael James Irwin ,  Domenico Tuzi ,  Umberto Siciliani ,  Alessandro Alilla ,  Andrea Giovanni Xotta ,  Chung-Ping Wu ,  Luigi Marchese ,  Pasquale Conenna ,  Joonwoo Nam ,  Ishani Bhatt ,  Fulvio Rori ,  Andrea D'Alessandro ,  Michele Piccardi ,  Aleksey Prozapas ,  Luigi Pilolli ,  Violante Moschiano

IPC分类号： H01L27/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

公开(公告)号：US20240071497A1

公开(公告)日：2024-02-29

申请号：US17898827

申请日：2022-08-30

申请人： Micron Technology, Inc.

发明人： Anna Maria Conti ,  Umberto Maria Meotto ,  Domenico Tuzi

IPC分类号： G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.