Invention Publication
- Patent Title: METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE
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Application No.: US18519200Application Date: 2023-11-27
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Publication No.: US20240105713A1Publication Date: 2024-03-28
- Inventor: Tetsuhiro TANAKA , Yutaka OKAZAKI
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi
- Priority: JP 15214050 2015.10.30
- The original application number of the division: US15991195 2018.05.29
- Main IPC: H01L27/07
- IPC: H01L27/07 ; H01G4/008 ; H01G4/10 ; H01G4/40 ; H01L27/12 ; H01L29/66 ; H01L29/786 ; H01L29/94 ; H05K1/18
Abstract:
A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
Information query
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