Invention Publication
- Patent Title: MULTI-STAGE MASK ETCH PROCESS
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Application No.: US17951532Application Date: 2022-09-23
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Publication No.: US20240105800A1Publication Date: 2024-03-28
- Inventor: Reza Bayati , Alison V. Davis , Ramy Ghostine , Matthew J. Prince
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/8234 ; H01L29/06 ; H01L29/786

Abstract:
Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.
Information query
IPC分类: