Invention Publication
- Patent Title: ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE
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Application No.: US18244782Application Date: 2023-09-11
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Publication No.: US20240112728A1Publication Date: 2024-04-04
- Inventor: Harsh RAWAT , Kedar Janardan DHORI , Dipti ARYA , Promod KUMAR , Nitin CHAWLA , Manuj AYODHYAWASI
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Main IPC: G11C11/418
- IPC: G11C11/418 ; G11C11/412 ; G11C11/419

Abstract:
A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.
Information query
IPC分类: