公开(公告)号：US20220020405A1

公开(公告)日：2022-01-20

申请号：US17375149

申请日：2021-07-14

Applicant: STMicroelectronics International N.V.

Inventor： Ashish KUMAR ,  Dipti ARYA

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C5/14

Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

公开(公告)号：US20240112728A1

公开(公告)日：2024-04-04

申请号：US18244782

申请日：2023-09-11

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Dipti ARYA ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  H03M1/12

Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.

公开(公告)号：US20240071480A1

公开(公告)日：2024-02-29

申请号：US18231461

申请日：2023-08-08

Applicant: STMicroelectronics International N.V.

Inventor： Ashish KUMAR ,  Dipti ARYA

IPC: G11C11/418

CPC classification number: G11C11/418

Abstract: Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.