公开(公告)号：US20240143239A1

公开(公告)日：2024-05-02

申请号：US18379373

申请日：2023-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Nitin CHAWLA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0655

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

公开(公告)号：US20230410892A1

公开(公告)日：2023-12-21

申请号：US18137261

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4085

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386564A1

公开(公告)日：2023-11-30

申请号：US18137159

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Nitin CHAWLA ,  Promod KUMAR ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

公开(公告)号：US20230012567A1

公开(公告)日：2023-01-19

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US20240112728A1

公开(公告)日：2024-04-04

申请号：US18244782

申请日：2023-09-11

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Dipti ARYA ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  H03M1/12

Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.

公开(公告)号：US20240071439A1

公开(公告)日：2024-02-29

申请号：US18233522

申请日：2023-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Nitin CHAWLA ,  Promod KUMAR ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/109 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

公开(公告)号：US20230386566A1

公开(公告)日：2023-11-30

申请号：US18137191

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386565A1

公开(公告)日：2023-11-30

申请号：US18136507

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/74

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/742

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

公开(公告)号：US20220130454A1

公开(公告)日：2022-04-28

申请号：US17483501

申请日：2021-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI

IPC: G11C11/417 ,  G11C11/412

Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.

公开(公告)号：US20250078883A1

公开(公告)日：2025-03-06

申请号：US18951392

申请日：2024-11-18

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.