Invention Publication
- Patent Title: INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES
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Application No.: US18535623Application Date: 2023-12-11
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Publication No.: US20240112952A1Publication Date: 2024-04-04
- Inventor: Hui Jae YOO , Tejaswi K. INDUKURI , Ramanan V. CHEBIAM , James S. CLARKE
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- The original application number of the division: US14038502 2013.09.26
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.
Public/Granted literature
- US12266568B2 Interconnect wires including relatively low resistivity cores Public/Granted day:2025-04-01
Information query
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