公开(公告)号：US20230130273A1

公开(公告)日：2023-04-27

申请号：US18088474

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Hui Jae YOO ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  James S. CLARKE

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20180211918A1

公开(公告)日：2018-07-26

申请号：US15925009

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20170084487A1

公开(公告)日：2017-03-23

申请号：US15126575

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Ramanan V. CHEBIAM ,  Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  James S. CLARKE ,  John J. PLOMBON

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20240112952A1

公开(公告)日：2024-04-04

申请号：US18535623

申请日：2023-12-11

Applicant: Intel Corporation

Inventor： Hui Jae YOO ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  James S. CLARKE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L21/76843 ,  H01L2224/45015 ,  H01L2924/0002

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20220238451A1

公开(公告)日：2022-07-28

申请号：US17718038

申请日：2022-04-11

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20190214559A1

公开(公告)日：2019-07-11

申请号：US16099173

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： James S. CLARKE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Tejaswi K. INDUKURI ,  Niloy MUKHERJEE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1675

Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

公开(公告)号：US20180248116A1

公开(公告)日：2018-08-30

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Satyarth SURI ,  Tejaswi K. INDUKURI

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/34 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20200286836A1

公开(公告)日：2020-09-10

申请号：US16881530

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20200090992A1

公开(公告)日：2020-03-19

申请号：US16582923

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Yuriy V. SHUSTERMAN ,  Flavio GRIGGIO ,  Tejaswi K. INDUKURI ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20200066967A1

公开(公告)日：2020-02-27

申请号：US16068078

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Satyarth SURI ,  Tejaswi K. INDUKURI ,  Robert B. TURKOT, JR. ,  James S. CLARKE

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: Damascene-based approaches for fabricating a pedestal for a magnetic tunnel junction (MTJ) device, and the resulting structures, are described. In an example, a magnetic tunnel junction (MTJ) device includes a metal line disposed in a dielectric layer disposed above a substrate, the metal line recessed below an uppermost surface of the dielectric layer. The MTJ device also includes a conductive pedestal disposed on the metal line and laterally adjacent to the dielectric layer. The MTJ device also includes a magnetic tunnel junction (MTJ) stack disposed on the conductive pedestal.