- 专利标题: ETCH STOP LAYER FOR METAL GATE CUT
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申请号: US17957106申请日: 2022-09-30
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公开(公告)号: US20240113106A1公开(公告)日: 2024-04-04
- 发明人: Sukru Yemenicioglu , Nikhil J. Mehta , Leonard P. Guler , Daniel J. Harris
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L27/088
- IPC分类号: H01L27/088 ; H01L21/8234
摘要:
An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.
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