INSTRUCTION SET ARCHITECTURE SUPPORT FOR AT-SPEED NEAR-MEMORY ATOMIC OPERATIONS IN A NON-CACHED DISTRIBUTED MEMORY SYSTEM
Abstract:
Systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
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