Invention Publication
- Patent Title: INSTRUCTION SET ARCHITECTURE SUPPORT FOR AT-SPEED NEAR-MEMORY ATOMIC OPERATIONS IN A NON-CACHED DISTRIBUTED MEMORY SYSTEM
-
Application No.: US18458462Application Date: 2023-08-30
-
Publication No.: US20240119015A1Publication Date: 2024-04-11
- Inventor: Shruti Sharma , Robert Pawlowski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F9/52

Abstract:
Systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
Public/Granted literature
- US3232026A Separation method using activated diffusion barriers Public/Granted day:1966-02-01
Information query