Invention Publication
- Patent Title: LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR
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Application No.: US18383816Application Date: 2023-10-25
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Publication No.: US20240136105A1Publication Date: 2024-04-25
- Inventor: Aleksey Khenkin , David Patten , Jun Yan
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- The original application number of the division: US17173486 2021.02.11
- Main IPC: H01F27/28
- IPC: H01F27/28 ; H01F17/00 ; H01F27/24

Abstract:
A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
Public/Granted literature
- US12217898B2 Method for constructing a solenoid inductor Public/Granted day:2025-02-04
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