-
公开(公告)号：US20250166881A1
公开(公告)日：2025-05-22
申请号：US18916413
申请日：2024-10-15
Inventor： Aleksey Khenkin , David Patten , Jun Yan
Abstract: A solenoid inductor of an IC package with active/passive devices constructed by a method including positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
-
公开(公告)号：US10252906B2
公开(公告)日：2019-04-09
申请号：US15788499
申请日：2017-10-19
Inventor： Roberto Brioschi , David Patten , Rkia Achehboune
Abstract: The application describes a package design for a MEMS transducer having an integrated circuit mounted within a chamber of the package. The integrated circuit may extend into a side wall recess of the package.
-
公开(公告)号：US12217898B2
公开(公告)日：2025-02-04
申请号：US18383816
申请日：2023-10-25
Inventor： Aleksey Khenkin , David Patten , Jun Yan
Abstract: A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
-
公开(公告)号：US10696545B2
公开(公告)日：2020-06-30
申请号：US16007799
申请日：2018-06-13
Inventor： Aleksey Sergeyevich Khenkin , David Patten
Abstract: The application describes a package for a MEMS transducer. The package has a package substrate having an acoustic port formed in the package substrate. The acoustic port comprises a first acoustic port volume portion and a second acoustic port volume portion, the first acoustic port volume portion being separated from the second acoustic port volume potion by a discontinuity in a sidewall of the substrate. The cross sectional area of the first acoustic port volume portion is greater than the cross sectional area of the second acoustic port volume portion. A barrier may be attached to the upper surface of the package substrate so as to seal or cover the acoustic port.
-
公开(公告)号：US11299392B2
公开(公告)日：2022-04-12
申请号：US16869075
申请日：2020-05-07
Inventor： Rkia Achehboune , Roberto Brioschi , Dimitris Drogoudis , David Patten
Abstract: The Application describes a substrate design for a MEMS transducer package. The substrate is defined by a conductive layer which forms the upper and lower surfaces of the substrate. The substrate is also provided with a conductive portion which is electrically isolated from the rest of the conductive layer. The conductive portion is supported between a first plane defined by the upper surface of the substrate and a second plane defined by the lower surface of the substrate by an electrically insulating moulding substance.
-
Patent Agency Ranking
公开(公告)号：US10469956B2
公开(公告)日：2019-11-05
申请号：US15852098
申请日：2017-12-22
Inventor： Aleksey Sergeyevich Khenkin , David Patten , Dimitris Drogoudis
Abstract: A MEMS transducer package comprising a substrate; a filter circuit for filtering RF signals, the filter circuit comprising a resistor and a capacitor; and an IPD chip; wherein at least a portion of the filter circuit is provided within the IPD chip.
-
公开(公告)号：US20240136105A1
公开(公告)日：2024-04-25
申请号：US18383816
申请日：2023-10-25
Inventor： Aleksey Khenkin , David Patten , Jun Yan
CPC classification number: H01F27/2804 , H01F17/0013 , H01F27/24 , H01F41/08
Abstract: A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
-
公开(公告)号：US11881343B2
公开(公告)日：2024-01-23
申请号：US17173486
申请日：2021-02-11
Inventor： Aleksey S. Khenkin , David Patten , Jun Yan
CPC classification number: H01F27/2804 , H01F17/0013 , H01F27/24 , H01F41/08
Abstract: A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform said positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
-
公开(公告)号：US20220384413A1
公开(公告)日：2022-12-01
申请号：US17303251
申请日：2021-05-25
Inventor： Aleksey Khenkin , Justin Richardson , Michael Robinson , David Patten
Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.
-
公开(公告)号：US11252513B2
公开(公告)日：2022-02-15
申请号：US16823588
申请日：2020-03-19
Inventor： Roberto Brioschi , Rkia Achehboune , David Patten
Abstract: The application relates to a MEMS transducer package comprising: a package substrate the package substrate comprising a substrate channel, the substrate channel comprising first and second channel portions, wherein the first portion extends in a first direction between a first channel opening in a side surface of the substrate and a junction between the first and second channel portions, and wherein the second portion extends in a second direction between said junction and a second channel opening at, or underlying, a substrate opening provided in an upper surface of the package substrate.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.013 seconds)
