Invention Publication
- Patent Title: CURRENT SHARING MISMATCH REDUCTION IN POWER SEMICONDUCTOR DEVICE MODULES
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Application No.: US18154722Application Date: 2023-01-13
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Publication No.: US20240136259A1Publication Date: 2024-04-25
- Inventor: Oseob JEON , Seungwon IM , Rajani Kumar THIRUKOLURI , Roveendra PAUL
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00 ; H01L23/538

Abstract:
In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.
Information query
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