公开(公告)号：US20240136259A1

公开(公告)日：2024-04-25

申请号：US18154722

申请日：2023-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Rajani Kumar THIRUKOLURI ,  Roveendra PAUL

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49562 ,  H01L23/5386 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/40225 ,  H01L2224/48225 ,  H01L2224/73221

Abstract: In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

公开(公告)号：US20240237216A9

公开(公告)日：2024-07-11

申请号：US18491456

申请日：2023-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Rajani Kumar THIRUKOLURI ,  Roveendra PAUL

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H05K1/11 ,  H05K2201/10166

Abstract: In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

公开(公告)号：US20240138069A1

公开(公告)日：2024-04-25

申请号：US18491456

申请日：2023-10-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Rajani Kumar THIRUKOLURI ,  Roveendra PAUL

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H05K1/11 ,  H05K2201/10166

Abstract: In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

公开(公告)号：US20200335414A1

公开(公告)日：2020-10-22

申请号：US15929662

申请日：2020-05-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Roveendra PAUL ,  Dukyong LEE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/40

Abstract: In one general aspect, an apparatus can include a module including a semiconductor die. The apparatus can include a heatsink coupled to the module and including a substrate, and a plurality of protrusions. The apparatus includes a cover defining a channel where the channel is outside of the module and the plurality of protrusions of the heatsink are disposed within the channel, and a sealing mechanism is disposed between the cover and the module is in contact with the module.

公开(公告)号：US20240064944A1

公开(公告)日：2024-02-22

申请号：US18364330

申请日：2023-08-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Roveendra PAUL ,  Hyungsoo KIM

IPC: H05K7/20

CPC classification number: H05K7/20927

Abstract: A package includes a power electronics module disposed between a first bracket and a second bracket with the power electronics module covering openings in the first bracket and the second bracket. Leak-proof joints are formed between surfaces of the power electronics module and the first bracket and the second bracket. A first cover beam is disposed on, and joined to, the first bracket to enclose a first cooling fluid channel for cooling fluid flow over the power electronics module. A second cover beam is disposed on, and joined to, the second bracket to enclose a second cooling fluid channel for cooling fluid flow over the power electronics module. The package includes end connectors that have input and output ports for cooling fluid flow through the first cooling fluid channel and the second cooling fluid channel.

公开(公告)号：US20230230895A1

公开(公告)日：2023-07-20

申请号：US18186842

申请日：2023-03-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Roveendra PAUL ,  Dukyong LEE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/40

CPC classification number: H01L23/3675 ,  H01L23/3735 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2023/4031

Abstract: In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.

公开(公告)号：US20190341327A1

公开(公告)日：2019-11-07

申请号：US15968353

申请日：2018-05-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Roveendra PAUL ,  Dukyong LEE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/40

Abstract: In one general aspect, an apparatus can include a module including a semiconductor die. The apparatus can include a heatsink coupled to the module and including a substrate, and a plurality of protrusions. The apparatus can include a cover including a channel where the plurality of protrusions of the heatsink are disposed within the channel, and can include a sealing mechanism disposed between the cover and the module.

公开(公告)号：US20250038066A1

公开(公告)日：2025-01-30

申请号：US18359259

申请日：2023-07-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh KRISHNAN ,  Chee Hiong CHEW ,  Yusheng LIN ,  Roveendra PAUL

IPC: H01L23/373 ,  H01L23/427

Abstract: In a general aspect, a semiconductor device assembly includes a metallic chamber configured to transfer thermal energy from a first surface of the metallic chamber to a second surface of the metallic chamber opposite the first surface, a thermally conductive polymer layer disposed on the first surface of the metallic chamber, a patterned metal layer disposed on the thermally conductive polymer layer, and at least one semiconductor die disposed on the patterned metal layer.

公开(公告)号：US20240128197A1

公开(公告)日：2024-04-18

申请号：US18487835

申请日：2023-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Olaf ZSCHIESCHANG ,  Oseob JEON ,  Jihwan KIM ,  Roveendra PAUL ,  Klaus NEUMAIER ,  Jerome TEYSSEYRE

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072

Abstract: In a general aspect, an assembly includes a panel of organic substrate core material having a cavity defined therein, a module substrate disposed in the cavity, and a semiconductor die disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material, and a metal layer. The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.

公开(公告)号：US20230225044A1

公开(公告)日：2023-07-13

申请号：US18154303

申请日：2023-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Roveendra PAUL ,  Jerome TEYSSEYRE

IPC: H05K1/02 ,  H05K1/18 ,  H03K17/687

CPC classification number: H05K1/0216 ,  H05K1/181 ,  H03K17/6871 ,  H05K2201/10166 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.