Invention Publication
- Patent Title: METHODS AND APPARATUS TO ELEVATE CIRCUIT NODES
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Application No.: US17977666Application Date: 2022-10-31
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Publication No.: US20240143882A1Publication Date: 2024-05-02
- Inventor: Paul Hack , Carlos Alberto Jimenez Chavez , Scot Zickel , Ilan Ronen , Koby Zand , Leonid Tsukerman , John Giacobbe
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F30/347
- IPC: G06F30/347 ; G06F30/343

Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes; identifier circuitry to: identify a node within the plurality of nodes for elevation; and identify a layer of an integrated circuit; port adder circuitry to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer; connector circuitry to modify the circuitry logic by connecting the signal port to the identified node; and layout planner circuitry to determine a layout of the integrated circuit based on the modified circuitry logic.
Information query