METHODS AND APPARATUS TO ELEVATE CIRCUIT NODES

    公开(公告)号:US20240143882A1

    公开(公告)日:2024-05-02

    申请号:US17977666

    申请日:2022-10-31

    CPC classification number: G06F30/347 G06F30/343

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes; identifier circuitry to: identify a node within the plurality of nodes for elevation; and identify a layer of an integrated circuit; port adder circuitry to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer; connector circuitry to modify the circuitry logic by connecting the signal port to the identified node; and layout planner circuitry to determine a layout of the integrated circuit based on the modified circuitry logic.

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